Field
The present disclosed technology generally relates to semiconductor fabrication and more particularly to a method of forming vertical channel devices.
Description of the Related Technology
There is a general objective in the semiconductor industry to scale integrated circuit (IC) devices, e.g., by reducing the area occupied by discrete devices such as transistors, and to correspondingly increase the device density per unit area. With the goal of providing even more area efficient circuit designs, new semiconductor devices are being developed. One type of area-efficient semiconductor device is a vertical channel transistor device, e.g., as vertical nanowire field effect transistors (FETs). In vertical nanowire FETs, due to the vertically oriented channel structure, the lateral footprint occupied by the gate length does not scale with a linewidth of the gate but instead scales with the gate thickness. In addition, the source and drain regions of a vertical transistor device are vertically displaced relative to each other. For these reasons, among others, vertical transistor devices enable dense device integrations.
To form functioning circuits, the gates and source/drains of the devices needs to make contact. However, due to the vertical orientation of the channel structures, contacting of the vertical channel structures may be more challenging than contacting of horizontal channel devices. Embodiments disclosed herein address these and other challenges associated with scaling IC devices.